1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices and methods of driving the same. More particularly, the present invention relates to an LCD device and a method of driving the same capable of effectively applying a charge sharing technique.
2. Discussion of the Related Art
Generally, light transmittance characteristics of liquid crystal cells within liquid crystal display (LCD) devices are controlled by video signals to display desired pictures. Active matrix-type LCDs are capable of displaying moving pictures and include a plurality of liquid crystal cells arranged in a matrix pattern, wherein each liquid crystal cell includes a pixel electrode and a switching device (i.e., a thin film transistor (TFT)).
FIG. 1 illustrates a related art LCD device.
Referring to FIG. 1, the related art LCD device typically includes an LCD panel 14 having m-number of data lines D1 to Dm perpendicularly crossing n-number of gate lines G1 to Gn, wherein liquid crystal cells (Clc) are defined at crossings of the data and gate lines; a plurality of TFTs arranged at the crossings of data and gate lines for driving corresponding liquid crystal cells; a data driving circuit 12 for supplying video signals to the data lines D1 to Dm; a gate driving circuit 13 for supplying scanning pulses to the gate lines G1 to Gn; and a timing controller 11 for controlling the data and gate driving circuits 12 and 13, respectively.
The LCD panel 14 generally includes an upper glass substrate separated from a lower glass substrate by liquid crystal material. The lower glass substrate supports the data lines D1 to Dm and the gate lines G1 to Gn. Arranged at each crossing of the data lines D1 to Dm and the gate lines G1 to Gn, the TFTs transmit video signals from the data lines D1 to Dm to the corresponding liquid crystal cell (Clc) in response to scanning pulses transmitted by the gate lines G1 to Gn. Each TFT includes a gate electrode connected to a corresponding one of the gate lines G1 to Gn, a source electrode connected to a corresponding one of the data lines D1 to Dm, and a drain electrode connected to a corresponding one of the pixel electrodes. Each liquid crystal cell (Clc) includes a storage capacitor Cst for maintaining a voltage charged therein for a predetermined amount of time. Storage capacitors Cst are provided between liquid crystal cells (Clc) connected to the nth gate line and a n−1th pre-stage gate line or between liquid crystal cells (Clc) connected to the nth gate line and a separate common storage line (not shown).
The data driving circuit 12 generally includes a plurality data driving integrated circuits, each of which includes a predetermined number of channels. Each data driving integrated circuit includes a shift register for sampling a clock signal, a register for temporarily storing data, a latch for storing one line of data in response to the clock signal outputted from the shift register and for simultaneously outputting the stored data, a digital-to-analog converter for selecting positive/negative gamma voltages corresponding to a value of the data outputted from the latch, a multiplexer for selecting one of the data lines D1 to Dm to apply analog data (i.e., a video signal that has been converted by the positive/negative gamma voltage), and an output buffer connected between the multiplexer and the selected data line. Such a data driving integrated circuit 12 is controlled by the timing controller 11 to supply video signals to the data lines D1 to Dm.
The gate driving circuit 13 generally includes a shift register for sequentially generating scanning pulses and a level shifter for shifting a voltage of each scanning pulse to a voltage level suitable for driving particular liquid crystal cells (Clc). Such a gate driving circuit 13 is controlled by the timing controller 11 to sequentially supply scanning pulses to the gate lines G1 to Gn in synchrony with the applied video signals.
The timing controller 11 employs vertical (V)/horizontal (H) signals and a clock signal (CLK) to generate gate control signals (GDC) that control the gate driving circuit 13 and data control signals (DDC) that control the data driving circuit 12. The DDC signals include a source start pulse (SSP), a source shift clock (SSC), a source output enable signal (SOE), and a polarity signal (POL). The GDC signals include a gate shift clock (GSC), a gate output enable signal (GOE) and a gate start pulse (GSP).
Many types of inversion driving methods (e.g., frame inversion, line inversion, column inversion method, and dot inversion) are known for use in driving the liquid crystal cells (Clc) of the LCD panel 14.
Referring to FIGS. 2A and 2B, in driving the liquid crystal cells (Clc) of the LCD panel 14 according to the frame inversion driving method, polarities of the video signals applied to each of the liquid crystal cells within the LCD panel 14 are inverted between frames.
Referring to FIGS. 3A and 3B, in driving the liquid crystal cells (Clc) of the LCD panel 14 according to the line inversion driving method, polarities of the video signals applied to adjacent rows of liquid crystal cells within LCD panel 14 are inverted. Additionally, polarities of the video signals applied to each of the liquid crystal cells within the LCD panel 14 are inverted between frames. The line inversion driving method undesirably induces a cross-talk phenomenon between adjacent rows of liquid crystal cells which is manifested by flickering in horizontal stripe patterns between adjacent rows of liquid crystal cells.
Referring to FIGS. 4A and 4B, in driving the liquid crystal cells (Clc) of the LCD panel 14 according to the column inversion driving method, polarities of the video signals applied to adjacent columns of liquid crystal cells within the LCD panel 14 are inverted. Additionally, polarities of the video signals applied to each of the liquid crystal cells within the LCD panel 14 are inverted between frames. Similar to the line inversion method, the column inversion driving method undesirably induces a cross-talk phenomenon between adjacent columns of liquid crystal cells which is manifested by flickering in vertical stripe patterns between adjacent columns of liquid crystal cells.
Referring to FIGS. 5A and 5B, in driving the liquid crystal cells (Clc) of the LCD panel 14 according to a one-dot inversion driving method, the polarity of the polarity signal POL is inverted during each horizontal period such that polarities of the video signals applied to adjacent columns and rows of liquid crystal cells within the LCD panel 14 are inverted. Additionally, polarities of the video signals applied to each of the liquid crystal cells within the LCD panel 14 are inverted between frames. More specifically, during odd-numbered frames as shown in FIG. 5A, liquid crystal cells within odd-numbered columns of odd-numbered rows, in addition to liquid crystal cells within even-numbered columns of even-numbered rows, are supplied with video signals having a positive polarity (+) while liquid crystal cells within even-numbered columns of odd-numbered rows, in addition to liquid crystal cells within odd-numbered columns of even-numbered rows, are supplied with video signals having a negative polarity (−). During even-numbered frames as shown in FIG. 5B, liquid crystal cells within odd-numbered columns of odd-numbered rows, in addition to liquid crystal cells within even-numbered columns of even-numbered rows, are supplied with video signals having a negative polarity (−) while liquid crystal cells within even-numbered columns of odd-numbered rows, in addition to liquid crystal cells within odd-numbered columns of even-numbered rows, are supplied with video signals having a positive polarity (+).
Referring to FIGS. 6A and 6B, in driving the liquid crystal cells (Clc) of the LCD panel 14 according to a two-dot inversion driving method, the polarity of the polarity signal POL is inverted during every two horizontal periods such that polarities of the video signals applied to adjacent columns and pairs of adjacent rows of liquid crystal cells within the LCD panel 14 are inverted. Additionally, polarities of the video signals applied to each of the liquid crystal cells within the LCD panel 14 are inverted between frames.
As described above, the one- and two-dot inversion driving methods minimize the aforementioned cross-talk phenomenon manifested in flicker patterns between the frames (or fields), dramatically improving a picture quality of the LCD panel 14. Because the one- and two-dot inversion driving methods require that the polarities of the video signals be inverted for every column and row (or every other row), however, a significant amount of power is required to drive the liquid crystal cells of the LCD panel 14. In order to reduce this excessive power consumption, data integrated circuits within the data driving circuit 12 include a related art charge sharing circuit 20, as shown in FIG. 7.
Referring to FIG. 7, a related art charge sharing circuit 20 generally includes a plurality of first switching devices SW1 connected between an output buffer 22 and the data lines D1 to Dm and a plurality of second switching devices SW2 connected between adjacent data lines D1 to Dm. Generally, the charge sharing circuit 20 can supply specific voltages to each of the data lines D1 to Dm during a first period and can supply a mean voltage to each of the data lines D1 to Dm during a second period, between consecutive first periods. By supplying the mean voltage between the first periods, the power consumption of the data driving circuit 12 may be beneficially reduced. A more detailed description of the operation for the charge sharing circuit 20 will now be described with reference to FIG. 8.
Referring to FIG. 8, during a low period of the source output enable signal SOE, i.e., a period during which video signals are to be supplied to the data lines D1 to Dm, the charge sharing circuit 20 turns the first switching devices SW1 on. Consequently, positive- and negative-polarity video signals are outputted from the output buffer 22 directly to the data lines D1 to Dm and a desired picture is displayed on the LCD panel 14.
Next, during a high period of the source output enable signal SOE, i.e., a period during which video signals are not supplied to the data lines D1 to Dm, the charge sharing circuit 20 turns the first switching devices SW1 off and turns the second switching devices SW2 on. Consequently, all of the data lines D1 to Dm become electrically connected to each other and, in what may be characterized as “charge sharing,” supply a voltage having a mean value between the positive- and negative-polarity voltages supplied to the data lines D1 to Dm during the low period of the source output enable signal SOE to the data lines D1 to Dm.
Accordingly, the related art “charge sharing” coincides with the high period of the source output enable signal SOE. By supplying the mean voltage (i.e., charge sharing) during each high period of the source output enable signal SOE, the differences in voltage values supplied to the data lines D1 to Dm by the first switching devices SW1 during the successive low periods of the source output enable signal SOE may be minimized. By minimizing the difference in voltage values applied to liquid crystal cells, the power consumption of the data driving circuit 12 used to drive the LCD panel 14 according to the one-dot inversion driving method may be reduced. However, the related art charge sharing circuit 20 described above does not effectively reduce the power consumption of the data driving circuit 12 used to drive the LCD panel 14 according to the two-dot inversion driving method for reasons that will be discussed with reference to FIG. 9.
Referring to FIG. 9, the related art charge sharing circuit 20 operates according to the state of the source output enable signal SOE—not according to the state of the polarity signal POL and the polarity of the video signal is inverted every two periods of the source output enable signal SOE, i.e., the high period of the polarity signal POL has a pulse width that overlaps consecutive high periods of the source output enable signal SOE. Therefore, and as identified at reference numeral 24, when a high period of the source output enable signal SOE does not coincide with inversion of a polarity signal POL, all of the data lines D1 to Dm become electrically connected to each other and voltages supplied to the data lines D1 to Dm become non-uniform between successive horizontal periods of the LCD device. As a result of this non-uniformity, power consumption of the data driving circuit undesirably increases.